2008
EMSS 2008 Proceeding
Modeling and simulation of a nanostructure for a single electron technology implementation
Authors: Cristian Ravariu, Adrian Rusu, Ala Bondarciuc, Florina Ravariu, Tudor Niculiu, Florin Babarada, Vlad Bondarciuc
Abstract
The Electronic Devices Simulators are valuable tools used in micro and nano-electronics labs. This paper analyses the electrical characteristics evolution, under the down-scaling sizes tendency of the SOI devices. A nanostructure sub-10nm Si film thickness with a vacuum cavity in the device body was simulated. The global current is a superposition of a tunnel current through the cavity and an inversion current at the film bottom. The tunnel source-drain current prevails in devices with sub 10nm film thickness and provides the ID-VDS characteristics with a minimum. For film thickness comprised between 200-10nm, the ID-VGS curves preserve similar shapes with a classical MOS/ SOI?s transfer characteristics. For sub 10nm film thickness, the shape of the ID-VGS characteristics tends to have a maximum, like in Single Electron Device SED.
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